The invention relates to integrated circuit processing. More particularly, the invention relates to optical correction for deep sub-micron ( less than 0.25 xcexcm) integrated circuit processes.
As integrated circuits (ICs) become more dense, the widths of lines and components, as well as the separation between lines becomes increasingly smaller. Currently, deep sub-micron ( less than 0.25 xcexcm) processes are being used. However, with deep sub-micron processes, silicon yield is affected by several factors including reticle/mask pattern fidelity, optical proximity effects, and diffusion and loading effects during resist and etch processing. Typical problems include line-width variations that depend on local pattern density and topology and line end pullback.
FIG. 1a is an exemplary deep sub-micron design layout. FIG. 1a represents the intended layout; however, because of the physics of deep sub-micron processing the resulting circuit is different than the design layout. FIG. 1b is an uncorrected structure based on the design of FIG. 1a. 
In the structure of FIG. 1b, line widths vary based on topology and density, which can detrimentially affect speed and accuracy of operation. Line edges are also shortened and rounded, which can break connections and cause circuit failure. U.S. Pat. No. 5,858,580 issued to Wang, et al. (xe2x80x9cthe xe2x80x3580 patentxe2x80x9d) discloses a method and an apparatus for reducing gate width from an original size to a reduced size that can be a sub-micron dimension.
The xe2x80x3580 patent reduces gate sizes from a first manufacturing process having a first minimum realizable dimension to a second manufacturing process having a second minimum realizable dimension. The second minimum realizable dimension is less than the first minimum realizable dimension. However, the xe2x80x3580 patent requires an integrated circuit layout to be laid out for a first process and then shrunk for use with a second process. What is needed is improved deep sub-micron processing that can operate on an original circuit layout.
A method and apparatus for generating a phase shifting mask and a trim mask for integrated circuit manufacture is described. A first mask is generated that defines a first region in a first layer of the integrated circuit. The first region is based, at least in part, on a region in a second layer of the integrated circuit. A second mask is generated that defines a second region in the first layer of the integrated circuit. The second region is also based, at least in part, on the region in the second layer of the integrated circuit. The second mask also removes artifacts generated by the first mask.